This invention relates to integrated circuits, and more particularly to circuitry for buffering signals propagating on an integrated circuit.
Some integrated circuits (“ICs”) must include circuitry for propagating a signal a relatively long distance on the IC and/or distributing the signal to multiple destinations throughout the IC. An example of this is a clock signal on a programmable logic device IC (“PLD”). In order for a signal to travel a long distance and/or to multiple destinations on the IC without undesirable loss of signal strength, the signal may need to be buffered at several locations along the circuitry that conveys it. IC fabrication process variations or other similar effects may cause buffers that are intended to operate identically from one IC to the next to in fact differ in performance. For example, it may be intended for the buffers on an IC to have rise and fall times (“Tr” and “Tf”, respectively) that are equal. In actual practice, however, on some of the ICs Tr may be greater that Tf, while on others of the ICs Tf may be greater than Tr. Especially for a signal that must pass successively through several buffers, this can have any of several undesirable consequences. If the signal is a clock signal, for example, the duty cycle of the signal can be undesirably altered and/or worst-case jitter can become undesirably large.